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Logic Design

Proposed Q&A site for site of Q&A for FPGAs, ASICs, Programmable Logic and correlated fields. All experience levels are welcome...
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21 Example Questions

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up vote 10 down vote
When your design does not meet timing, what do you do first? Change the design/HDL, or try to tweak the tools to try harder?
added by woliveirajr Oct 11 '12 at 17:08
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up vote 10 down vote
How can I reduce the tool effort required to route a synchronous reset in an FPGA design?
added by woliveirajr Oct 11 '12 at 17:10
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up vote 10 down vote
When simulating a VHDL FPGA design, how can I read simulation data from a text file?
added by mjcopple, edited by Renan Feb 19 at 0:08
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up vote 10 down vote
How do I know when I've used enough flip-flops to buffer an external signal to prevent meta-stability?
added by dave Nov 1 '12 at 11:31
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This question is more open-ended than it may at first seem as it depends on many factors and is ultimately statistical - you cannot completely guarantee there won't be any meta-stability, you just reduce the MTBF by orders of magnitude. – Jxj Feb 9 at 7:13
up vote 10 down vote
What is the most efficient way (in terms of logic use) to create a divide-by-N circuit?
added by Renan Nov 5 '12 at 21:00
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up vote 10 down vote
How can I develop for [FPGA] using only open-source software?
added by Renan Nov 5 '12 at 21:02
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up vote 10 down vote
Where I can find a very simple example of a complete CPU for experiments using an FPGA?
added by muriloq Dec 6 '12 at 23:49
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up vote 9 down vote
Why most of the hobbyist / open source projects use VHDL instead of Verilog?
added by muriloq Dec 6 '12 at 23:51
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2  
I don't know if that's a fact. I would rephrase to: "What are the advantages resp. disadvantages of VHDL vs. Verilog for hobbyist/open source projects?" – stevenvh Jan 15 at 19:49
up vote 7 down vote
I just added a carry-save adder[1] to my FFT core in an attempt to improve performance. Why is it making no difference?
added by finnw Nov 27 '12 at 19:10
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[1]:en.wikipedia.org/wiki/Carry-save_adder – finnw Nov 27 '12 at 19:10
up vote 6 down vote
What's faster than a ripple carry adder for add two numbers together in an FPGA?
added by Nick ODell Mar 17 at 21:36
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up vote 4 down vote
What is wrong with this implementation of [SPI] in [VHDL]?
added by Renan Dec 6 '12 at 23:55
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up vote 3 down vote
Why are using 'if/else' statements sometimes considered bad or dangerous in verilog?
added by Tim Feb 18 at 20:30
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up vote 1 down vote
I wish to create a Cray XD1 like machine - it used FPGA boards to do the heavy lifting - what hardware / software would I use to accomplish that today
added by user1172468 Nov 5 '12 at 18:29
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up vote 1 down vote
What are the differences between Nexys™3 Spartan-6 FPGA Board and Spartan-3 Board?
added by akram Dec 6 '12 at 4:42
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up vote 1 down vote
How can I fix timing on my 'ready' handshake signal that must advance a very long pipelined datapath?
added by Tim Feb 14 at 15:50
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up vote 0 down vote
Using Altera Quartus on Debian?
added by sharksfan98 Feb 18 at 23:42
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up vote 0 down vote
PLB vs AXI. What is the difference?
added by Val Mar 30 at 14:33
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up vote 0 down vote
What's the best way to calculate an FFT on an FPGA?
added by Nick ODell Apr 23 at 23:18
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up vote 0 down vote
What is a purpose of MAP? I see that XST already performs the LUT-mapping while PAR places tehm.
added by Val May 16 at 14:45
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up vote -1 down vote
How do I use the "volatile" keyword?
added by woliveirajr Oct 11 '12 at 17:08
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2  
Is that not a general programming question? – Andrew Nov 2 '12 at 6:03
2  
This is best asked on Stack Overflow - it's to do with programming. – dave Nov 2 '12 at 6:49
up vote -1 down vote
Which programming language should one use? Verilog, VHDL, SystemVerilog or something else?
added by Jxj Feb 9 at 7:15
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