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Registered User

name Tim
member for 1 year
seen Sep 26 '13 at 15:15
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location San Jose, CA
age 28

Professional ASIC engineer with experience in RTL design, Verilog, synthesis, power, and timing issues on billion+ gate ICs.

Other hobbies include:

  • Computer Graphics
  • Android Programming
  • C++ Programming

Personal released projects:

Portfolio Map-----------Electron Flux

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