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name	Tim
member for	3 months
seen	May 8 at 19:17
website	stackoverflow.com/users/1236185/tim
location	San Jose, CA
age	27

Professional ASIC engineer with experience in RTL design, Verilog, synthesis, power, and timing issues on billion+ gate ICs.

Other hobbies include:

Computer Graphics
Android Programming
C++ Programming

Personal released projects:

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Logic Design

For site of Q&A for FPGAs, ASICs, Programmable Logic and correlated fields. All experience levels are welcome...

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Logic Design: Why are using 'if/else' statements sometimes considered bad or dangerous in verilog?

Logic Design: How can I fix timing on my 'ready' handshake signal that must advance a very long pipelined datapath?

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